1. Technical Field
The present invention relates to a drive circuit of a liquid crystal display device, and more particularly to a drive circuit having a shift register using an amorphous silicon (a-Si) thin film transistor.
2. Related Art
A liquid crystal display (LCD) is a display device for use with a television or a computer. The LCD controls light transmittance of a liquid crystal using an electric field to display a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type and a drive circuit for driving the liquid crystal display panel.
The liquid crystal display panel includes a liquid crystal cell formed at each area which is defined by intersecting gate lines and data lines. A thin film transistor (hereinafter, referred to as “TFT”) is connected between a gate line and a data line and a pixel electrode is included in the liquid crystal cell. The TFT supplies a data signal from the data line to the pixel electrode in response to a scan signal from the gate line. The liquid crystal cell controls a light transmittance by having liquid crystal molecules with dielectric anisotropy rotate in accordance with a voltage difference between the pixel electrode and a common electrode. As a result, gray levels may be displayed.
The drive circuit includes a gate driver for driving the gate lines, and a data driver for driving the data lines. The gate driver sequentially supplies the scan signal to the gate lines. The data driver converts a digital data into an analog data signal to supply the analog data signal to the data line whenever the scan signal is supplied. The gate driver includes a shift register for sequentially generating the scan signal. The data driver also includes a shift register for generating sequential sampling signals which make the data signal from the outside sampled sequentially.
FIG. 1 illustrates a shift register 10 of the related art which includes 1st to nth stages that are connected in cascade to a start pulse Vst input line. The 1st to nth stages of the shift register shown in FIG. 1 are commonly supplied with first and second clock signals C1, C2 along with high-level and low-level driving voltages VDD, VSS. The 1st to nth stages of the shift register 10 are supplied with the start pulse Vst and an output signal of the previous stage. The 1st stage outputs a first output signal Out1 in response to the start pulse Vst and the first and second clock signals C1, C2. The 2nd to nth stages output 2nd to nth output signals in response to the output signal of the previous stage and the first and second clock signals C1, C2, respectively. The 1st to nth stages may have an identical circuit configuration and sequentially shift the start pulse Vst to output it in response to the first and second clock signals C1, C2. For use with a gate driver, the 1st to nth output signals Out1 to Outn from the 1st to nth stages are supplied as the scan signal for sequentially driving the gate lines of the liquid crystal display panel. Alternatively, for use with a data driver, the 1st to nth output signals Out1 to Outn may be supplied as the sampling signal for sequentially sampling a video signal within the data driver.
FIG. 2 is a circuit diagram illustrating configuration of one of the stages shown in FIG. 1. The stage 15 shown in FIG. 2 includes an output buffer part 30 having a pull-up TFT Tpu which outputs a clock signal C to an output line under control of a Q node. The output buffer part 30 further includes a pull-down TFT Tpd which outputs the low-level driving voltage VSS to the output line under control of a QB node. The stage also includes a controller 20 for controlling the Q node and the QB node.
The controller 20 charges the Q node with the output signal of the previous stage, i.e., start pulse Vst, to make the pull-up TFT Tpu output a high-state voltage of the clock signal C as an output signal Out_i. Additionally, the controller 20 discharges the Q node and charges the QB node by the clock signal C to make the pull-down TFT Tpd output the low-level voltage VSS as the output signal Out_i. The pull-down TFT Tpd is turned off when the pull-up TFT Tpu is turned on. As a result, the low-level voltage VSS is output as the output signal Out_i. To this end, the QB node may remain in a high state for the period that the pull-down TFT Tpd is on by the controller 10. During this time, the pull-down TFT Tpd may experience malfunctions because it may be subject to excessive gate bias stress. As a result, a threshold voltage Vth of the pull-down TFT Tpd may be changed.